Description: uart的vhdl实现代码
分模块设计和状态机设计
不错的，用它没错-UART achieve the VHDL code modular design and state machine design good, the right to use it Platform: |
Size: 10594 |
Author:王平 |
Hits:
Description: uart的vhdl实现代码
分模块设计和状态机设计
不错的，用它没错-UART achieve the VHDL code modular design and state machine design good, the right to use it Platform: |
Size: 10240 |
Author:王平 |
Hits:
Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART. Platform: |
Size: 1106944 |
Author:xiao cao |
Hits:
Description: 简单的uart状态机的编写，作为课程设计的资料，适于入门-UART simple state machine to prepare, as a curriculum design information, suitable for entry- Platform: |
Size: 587776 |
Author:李欣 |
Hits:
Description: UART是一种广泛应用于短距离、低速、低成本通信的串行传输接口.由于常用UART芯片比较复杂且移植性差,提出一种采用可编程器件FPGA实现UART的方法, 实现了对UART的模块化设计.首先简要介绍UART的基本特点,然后依据其系统组成设计顶层模块,再采用有限状态机设计接收器模块和发送器模块,所有功能的实现全部采用VHDL进行描述,并用Modelsim软件对所有模块仿真实现.最后将UART的核心功能集成到FPGA上,使整体设计紧凑,小巧,实现的UART功能稳定、可靠. -UART is a widely used short-range, low-speed, low-cost serial transmission interface communication. Because of the complexity of common UART chip and poor transplant, using a programmable FPGA devices to achieve UART way of the realization of the UART modular design. First of all, a brief introduction of the basic characteristics of UART, and then according to their top-level module system design, and then the design of finite state machine receiver module and transmitter module, the realization of all the features to describe the use of VHDL and Modelsim software used Simulation of all modules. Finally, the UART core functionality into the FPGA, so that the overall design of compact, compact, the UART function of the realization of stable and reliable. Platform: |
Size: 38912 |
Author:徐明宝 |
Hits:
Description: 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to achieve, and deposited LPM_RAM. The design of a UART module (state machine is realized), the data can be sent to the PC machine. Platform: |
Size: 214016 |
Author:deadtomb |
Hits:
Description: 自己写的一个uart驱动代码，是一个工程文件，适合初学者，里面的状态机的写法十分值得学习-To write a uart driver code, is a project file, suitable for beginners, which the wording of the state machine is worth learning Platform: |
Size: 342016 |
Author:JackChen |
Hits:
Description: 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。 已通过测试。
-FPGA-based signal acquisition and spectrum analysis, using VHDL prepared compression bag Quartus engineering. AD sampling using the state machine to achieve now, and into the LPM_RAM. Design a UART module (which is also the state machine), the data is sent to the PC. Has passed the test. Platform: |
Size: 215040 |
Author:l2003l |
Hits:
Search - UART state machine VHDL